The present invention relates to a clock signal supplying device use in an electronic computer, etc., and in particular, to a clock signal supplying device suitably used for a clock supplying system in a large scale electronic computer dealing with high speed operations.
FIG. 1 shows a prior art example of the clock signal supplying device used in an electronic computer, in which reference numeral 10 is a clock signal generating section; 20 is a device to which clock signals are distributed; and 30 represents cables connecting section 10 and device 20. Further, 40 is a lower rank destination of distribution disposed in a destination of distribution 20, and 50 is a further lower rank destination of distribution disposed in the lower rank destination of distribution 40 in which there are disposed still further terminal destinations of distribution. Concretely speaking, 20 is a box; 40 is a wiring board (module); 50 is an LSI chip; and the terminal destinations of distribution are flipflops. This device divides an original clock signal extracted from a high frequency oscillator 11 into clock signals having a predetermined frequency and a predetermined number of phases as needed by making the original clock signal pass through a frequency divider 12 and distributing the divided signal to the terminal destinations of distribution through several stages of buffer LSIs such as 13, 21, 41, etc., cables 30, etc. It there are fluctuations in the signal propagation time in the buffer circuits and the cables, they appear in each destination of distribution as fluctuations in the phase of the clock signal (called also clock skew). Since a great clock skew prevents the raising the speed of the electronic computer, it is necessary to reduce the clock skew by regulating the phase by some method.
As a prior art phase regulation method for a clock signal in a large scale electronic computer, it was a usual practice that the waveform of the clock signal in each of destinations of the distribution was observed by means of an oscilloscope, etc., and the phase was adjusted to a predetermined value, e.g., by manually exchanging a delay element 14 in FIG. 1.
Further, a method by which exchange of the delay element is made unnecessary by varying the delay time by means of a control signal is disclosed in a Japanese patent application, JP-A-61-39650, filed July 28, 1984 by Fujitsu Limited and laid open Feb. 25, 1986.
Additionally, as a method by which no oscilloscope is used, another method is disclosed in a Japanese patent application, JP-A-61-39619 filed July 30, 1984 by Nihon Electric Co., Ltd., and laid open Feb. 25, 1986, in which a ring oscillator composed of a clock supplying circuit is used, and the oscillation frequency thereof is adjusted to a predetermined value while detecting the signal delay time of the clock supplying circuit therefrom.
In the case where the phase regulation of the clock signal is effected by means of an oscilloscope, etc., the regulation is fairly tedious, and therefore it is not possible to increase by much the number of positions to be regulated. Consequently, after the phase has been regulated at a restricted number of relay positions, the signal cannot help being transmitted therefrom to the terminal destinations of distribution without phase regulations. The fluctuations in the signal propagation time for the part transmitted without phase regulation form a decrease limit in the clock skew. Further, since reflection, attenuation in the amplitude, etc. produced in the cable become remarkable with the increasing frequency of the clock signal, the phase regulation of the clock signal having a high frequency was originally difficult.
For example, in FIG. 1, the cable 30 from the clock source 10 to each of the destinations of distribution 20 in the large scale electronic computer is necessarily about 2 to 4 m, because the box cannot be too small. On the other hand, since the clock source cannot be too large, the outer diameter of the cable is limited to a size smaller than about 2 to 3 mm. When a clock signal having a frequency higher than about 100 MHz is transmitted through such a cable, attenuation appears in the amplitude of the signal. In particular, if the frequency exceeds several hundreds of MHz, the amplitude of the signal is reduced by below about one half. Together with this, the phase regulation of the clock signal becomes more difficult.
Further, in the case where a buffer LSI chip is exchanged because of trouble, etc., the phase regulation should be reexecuted every time.
By the method disclosed in JP-A-61-39650, although the delay element should not be exchanged every time, it is necessary to observe whether the clock signal has a desired phase or not. Further, since the delay time is controlled by regulating an analog voltage, if this control voltage is varied by noise, this appears as a clock skew.
On the other hand, by the method disclosed in JP-A-61-39619, it is necessary to make all the propagation times uniform in signal paths for feeding back the signal from the destinations of distribution to the initial input point, and finally, the clock skew is not finally reduced, and less propagation times are made uniform in a number of signal paths.